In recent years, digital cameras incorporating solid-state imaging apparatuses have been widely available. FIG. 5 is a diagram illustrating a configuration of a pixel of a solid-state imaging apparatus according to a conventional technique disclosed in Patent Literature (PTL) 1. As illustrated in FIG. 5, a pixel 1 includes a photodiode 2, an amplifying transistor 3, a transfer transistor 5, a reset transistor 6, a selection transistor 7, and a capacitor 17. Moreover a floating diffusion portion (FD portion) 4 is provided in the pixel 1.
A transistor 15 has a gate connected to a control line 16, and has a drain and a source connected to a signal output line 12 and a power supply, respectively. The control line 16 is a control line for controlling a potential of the signal output line 12 by applying a signal (pulse) to a gate of the transistor 15.
Next, an operation of the pixel illustrated in FIG. 5 will be described.
FIG. 6 is a timing chart for explaining the operation of the pixel illustrated in FIG. 5
In FIG. 6, signals SC, RC, TC, and VC are drive pulse signals to be applied via control lines 10, 9, 8, and 16 to transistors 7, 6, 5, 15, respectively, and potentials FD and SO indicate potentials of the FD portion 4 and the signal output line 12, respectively. It should be noted that each of the transistors 7, 6, and 5 in FIG. 5 is an N-channel type MOS transistor. When a gate potential is at a high level (“H”), the transistor becomes an ON state. When a gate potential is at a low level (“L”), the transistor becomes an OFF state. Moreover, the transistor 15 is a P-channel type MOS transistor. When a gate potential is at “H”, the transistor 15 becomes an OFF state. When a gate potential is at “L”, the transistor 15 becomes an ON state.
According to a configuration of the solid-state imaging apparatus according to the conventional technique, at a time when signal charges are transferred from the photodiode 2 to the FD portion 4, that is, during a period in which the signal TC to be supplied to the gate of the transfer transistor 5 via the control line 8 becomes “H” (time T15 to time T16), by putting the transistor 15 in an ON state, the potential SO of the signal output line 12 which supplies an output potential corresponding to the reset potential is set to a power supply potential, and the potential FD of the FD portion 4 capacitively coupled with the signal output line 12 by a potential fluctuation of this signal output line 12 is increased by ΔV1.
With this, since a condition for outputting a saturation voltage Vsat is (Vrs−Vsat+ΔV1)>Vd, a value of Vd that determines the limit of the saturation voltage can be set larger than before, and it is possible to obtain a larger saturation voltage. Therefore, it is possible to provide a method for driving a complementary metal-oxide-semiconductor (CMOS) type solid-state imaging apparatus that realizes a high dynamic range, and a dynamic range can be higher than that of the conventional CMOS type solid-sate imaging apparatus.